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information furnished by analog devices is be lieved to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or oth- erwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. t el: 781/329-4700 www.analog.com fa x: 781/326-8703 ?2003 analog devices, inc. all rights reserved. AD9991 10-bit ccd signal processor with precision timing ? generator features 6-phase vertical transfer clock support correlated double sampler (cds) 6 db to 42 db 10-bit variable gain ampli er (vga) 10-b it 27 mhz a/d converter black level clamp with variable level control complete on-chip timing generator precision timing core with 800 ps resolution on-chip 3 v horizontal and rg drivers 2-phase and 4-phase h-clock modes electronic and mechanical shutter modes on-chip driver for external crystal on-chip sync generator with external sync input 56-lead lfcsp package applications digital still cameras digital video camcorders industrial imaging general description the AD9991 is a highly integrated ccd signal processor for digital still camera and camcorder applications. it includes a complete analog front end with a/d conversion, combined with a full-function programmable timing generator. the timing genera- tor is capable of supporting both 4- and 6-phase vertical clocking. a precision timing core allows adjustment of high speed clocks with 800 ps resolution at 27 mhz operation. the AD9991 is speci ed at pixel rates of up to 27 mhz. the analog front end includes black level clamping, cds, vga, and a 10-bit a/d converter. the timing generator provides all the necessary ccd clocks: rg, h-clocks, v-clocks, sensor gate pulses, substrate clock, and substrate bias control. operation is programmed using a 3-wire serial interface. p ackaged in a space-saving 56-lead lfcsp, the AD9991 is speci- ed over an operating temperature range of ?0? to +85?. functional block diagram AD9991 cds vga clamp 10-bit adc 10 dclk mshut strobe clo cli dout vref 6db to 42db horizontal drivers v- h control 4 6 5 rg h1?4 v1?6 vsg1?sg5 vrt vrb precision timing generator sync generator internal clocks vsub subck hd vd sync internal registers sl sck data ccdin rev. 0
AD9991 ?2? t able of contents specifications ............................................................... 3 digital specit cations .......................................................... 3 analog specit cations ........................................................... 4 timing specit cations ........................................................... 5 absolute maximum ratings ..................................... 5 pa ckage thermal characteristics ...................... 5 ordering guide ............................................................. 5 pin configuration ....................................................... 6 pin function descriptions....................................... 6 terminology .................................................................. 7 equivalent circuits.................................................... 7 typical performance characteristics ............. 8 system overview............................................................ 9 precision timing high speed timing generation .................................................................... 10 timing resolution ............................................................. 10 high speed clock programmability.................................... 10 h-driver and rg outputs ................................................. 11 digital data outputs ........................................................ 11 horizontal clamping and blanking ................. 13 individual clpob and pblk patterns .............................. 13 individual hblk patterns ................................................. 13 generating special hblk patterns .................................... 14 generating hblk line alteration ..................................... 14 horizontal timing sequence example ............. 15 vertical timing generation ................................. 16 ve r tical pattern groups ...................................................... 17 ve r tical sequences.............................................................. 18 complete field: combining v-sequences ........................... 19 generating line alternation for v-sequence and hblk...... 20 second v-pattern group during vsg active line................ 20 sweep mode operation...................................................... 21 multiplier mode ................................................................ 21 ve r tical sensor gate (shift gate) patterns ........................... 22 mode register ................................................................ 23 vertical timing example ....................................... 24 important note about signal polarities ............................... 24 shutter timing control ........................................ 26 normal shutter operation ................................................. 26 high precision shutter operation....................................... 26 low speed shutter operation ............................................ 26 subck suppression ......................................................... 27 readout after exposure...................................................... 27 using the trigger register ............................................ 27 vsub control ................................................................... 28 mshut and strobe control ........................................ 28 trigger register limitations ......................................... 29 exposure and readout example.......................... 30 analog front end description and operation ......................................................... 31 dc restore ..................................................................... 31 correlated double sampler............................................... 31 va r iable gain amplit er .................................................... 31 a/d converter .................................................................. 31 optical black clamp......................................................... 32 digital data outputs ......................................................... 32 power-up and synchronization........................... 33 recommended power-up sequence for master mode......... 33 generating software sync without external sync signal ................................................... 33 sync during master mode operation...............................34 po w er-up and synchronization in slave mode.................... 34 standby mode operation ........................................ 34 circuit layout information ................................. 36 serial interface timing........................................... 37 register address banks 1 and 2.......................................... 38 updating of new register values ........................................ 39 complete listing of register bank 1 ............... 40 complete listing of register bank 2 ............... 43 outline dimensions.................................................. 59 rev. 0 ?3? AD9991?specifications p arameter mi n typ max unit temperature range operating 20 +85 ? storage ?5 +150 ? power supply voltage a vdd (afe analog supply) 2.7 3.0 3.6 v tcvdd (timing core analog supply) 2.7 3.0 3.6 v rgvdd (rg driver) 2.7 3.0 3.6 v hvdd (h1?4 drivers) 2.7 3.0 3.6 v drvdd (data output drivers) 2.7 3.0 3.6 v d vdd (digital) 2.7 3. 0 3.6 v power dissipation (see tpc 1 for power curves) 27 mhz, typ supply levels, 100 pf h1?4 loading 270 mw po w er from hvdd only * 100 mw standby 1 mode 105 mw standby 2 mode 10 m w standby 3 mode 0.5 mw maximum clock rate (cli) 27 mhz * the total power dissipated by the hvdd supply may be approximated using the equation to tal hvdd power = [ c load hvdd pixel frequency ] hvdd number of h-outputs used reducing the h-loading, using only two of the outputs, and/or using a lower hvdd supply will reduce the power dissipation. speci cations subject to change without notice. digital specifications p arameter symbol min typ max unit logic inputs high level input voltage v ih 2.1 v low level input voltage v il 0.6 v high level input current i ih 10 ? low level input current i il 10 ? input capacitance c in 10 pf logic outputs (except h and rg) high level output voltage @ i oh = 2 ma v oh 2.2 v low level output voltage @ i ol = 2 ma v ol 0.5 v rg and h-driver outputs (h1?4) high level output voltage @ max current v oh vdd ?0.5 v low level output voltage @ max current v ol 0.5 v maximum output current (programmable) 30 ma maximum load capacitance (for each output) 100 pf speci cations subject to change without notice. (rgvdd = hvdd = dvdd = drvdd = 2.7 v to 3.6 v, c l = 20 pf, t min to t max , un less oth er wise noted.) rev. 0 ?4? AD9991 analog specifications p arameter min typ max unit notes cds * allowable ccd reset transient 500 mv max input range before saturation 1.0 v p-p max ccd black pixel amplitude ?0 mv v ariable gain amplifier (vga) gain control resolution 1024 steps gain monotonicity guaranteed gain range min gain (vga code 0) 6 db max gain (vga code 1023) 42 db black level clamp clamp level resolution 256 steps clamp level measured at adc output. min clamp level (code 0) 0 lsb max clamp level (code 255) 63.75 lsb a/d converter resolution 10 bits differential nonlinearity (dnl) ?.0 ?.5 +1.0 lsb no missing codes guaranteed full-scale input voltage 2.0 v vo lt a ge reference reference top voltage (reft) 2.0 v reference bottom voltage (refb) 1.0 v system performance includes entire signal chain. gain accuracy low gain (vga code 0) 5.0 5.5 6.0 db gain = (0.0 351 code) + 6 db max gain (vga code 1023) 40.5 41.5 42.5 db peak nonlinearity, 500 mv input signal 0.2 % 12 db gain applied . total output noise 0.25 lsb rms ac grounded input, 6 db gain applied. power supply rejection (psr) 50 db measured with step change on supply. * input signal characteristics de ned as follows: 50mv max optical black pixel 500mv typ reset transient 1v max input signal range speci cations subject to change without notice. (avdd = 3.0 v, f cli = 27 mhz, typical timing speci? cations, t min to t max , unless otherwise noted.) rev. 0 AD9991 ?5? timing specifications (c l = 20 pf, avdd = dvdd = drvdd = 3.0 v, f cli = 27 mhz, unless otherwise noted.) p arameter symbol min typ ma x unit master clock, cli (figure 4) cli clock period t conv 37 ns cli high/low pulsewidth 14.8 18.5 21 .8 ns delay from cli rising edge to internal pixel position 0 t clidly 6 ns afe clpob pulsewidth 1, 2 (figures 9 and 14) 2 20 pixels afe sample location 1 (figure 7) shp sample edge to shd sample edge t s1 17 18.5 ns d ata outputs (figures 8a and 8b) output delay from dclk rising edge 1 t od 8 ns pipeline delay from shp/shd sampling to dout 11 cycles serial interface (figures 40a and 40b) maximum sck frequency f sclk 10 mhz sl to sck setup time t ls 10 ns sck to sl hold time t lh 10 ns sdata valid to sck rising edge setup t ds 10 ns sck falling edge to sdata valid hold t dh 10 ns sck falling edge to sdata valid read t dv 10 ns notes 1 pa rameter is programmable. 2 minimum clpob pulsewidth is for functional operation only. wider typical pulses are recommended to achieve good clamp performan ce. speci cations subject to change without notice. absolute maximum ratings * with respect p arameter to min max unit a vdd avss ?.3 +3.9 v tcvdd tcvss ?.3 +3.9 v hvdd hvss ?.3 +3.9 v rgvdd rgvss ?.3 +3.9 v d vdd dvss ?.3 +3.9 v drvdd drvss ?.3 +3.9 v rg output rgvss ?.3 rgvdd + 0.3 v h1?4 output hvss ?.3 hvdd + 0.3 v digital outputs dvss ?.3 dvdd + 0.3 v digital inputs dvss ?.3 dvdd + 0.3 v sck, sl, sdata dvss ?.3 dvdd + 0.3 v reft, refb, ccdin avss ?.3 avdd + 0.3 v junction temperature 150 ? lead temperature, 10 sec 350 ? * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions above those listed in the operational sections of this speci cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise speci ed, all other voltages are referenced to gnd. pa ckage thermal characteristics thermal resistance ja = 25?/w * * ja is measured using a 4-layer pcb with the exposed paddle soldered to the board. ordering guide temperature package package model range description option AD9991kcp ?0? to +85? lfcsp cp-56 AD9991kcprl ?0? to +85? lfcsp cp-56 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily ac cu mu late on the human body and test equipment and can discharge without detection. although the AD9991 features proprietary esd pro tec tion circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pre cau tions are rec om mend ed to avoid per for mance deg ra da tion or loss of functionality. rev. 0 AD9991 ?6? pin configuration top view AD9991 pin 1 identifier 42 sdi 41 sl 40 refb 39 reft 38 avss 37 ccdin 36 avdd 35 cli 34 clo 33 tcvdd d3 1 d4 2 d5 3 d6 4 d7 5 d8 6 d9 7 drvdd 8 drvss 9 vsub 10 56 d2 55 d1 54 d0 53 nc 52 nc 51 dclk 50 hd 49 dvdd 48 dvss 47 vd v4 15 v5 16 v6 17 vsg1 18 vsg2 19 vsg3 20 vsg4 21 vsg5 22 h1 23 h2 24 subck 11 v1 12 v2 13 v3 14 hvss 25 hvdd 26 h3 27 h4 28 32 tcvss 31 rgvdd 30 rg 29 rgvss 46 sync 45 strobe 44 mshut 43 sck pin mnemonic type 2 description 1 d3 do data output 2 d4 do data output 3 d5 do data output 4 d6 do data output 5 d7 do data output 6 d8 do data output 7 d9 do data output (msb) 8 drvdd p data output driver supply 9 drvss p data output driver ground 10 vsub do ccd substrate bias 11 subck do ccd substrate clock (e-shutter) 12 v1 do ccd vertical transfer clock 1 13 v2 do ccd vertical transfer clock 2 14 v3 do ccd vertical transfer clock 3 15 v4 do ccd vertical transfer clock 4 16 v5 do ccd vertical transfer clock 5 17 v6 do ccd vertical transfer clock 6 18 vsg1 do ccd sensor gate pulse 1 19 vsg2 do ccd sensor gate pulse 2 20 vsg3 do ccd sensor gate pulse 3 21 vsg4 do ccd sensor gate pulse 4 22 vsg5 do ccd sensor gate pulse 5 23 h1 do ccd horizontal clock 1 24 h2 do ccd horizontal clock 2 25 hvss p h1?4 driver ground 26 hvdd p h1?4 driver supply 27 h3 do ccd horizontal clock 3 28 h4 do ccd horizontal clock 4 29 rgvss p rg driver ground 30 rg do ccd reset gate clock 31 rgvdd p rg driver supply 32 tcvss p analog ground for timing core 33 tcvdd p analog supply for timing core 34 clo do clock output for crystal 35 cli di reference clock input pin mnemonic type 2 description 36 avdd p analog supply for afe 37 ccdin ai ccd signal input 38 avss p analog ground for afe 39 reft ao voltage reference top bypass 40 refb ao voltage reference bottom bypass 41 sl di 3-wire serial load pulse 42 sdi di 3-wire serial data input 43 sck di 3-wire serial clock 44 mshut do mechanical shutter pulse 45 strobe do strobe pulse 46 sync di external system sync input 47 vd dio vertical sync pulse (input for slave mode, output for master mode) 48 dvss p digital ground 49 dvdd p power supply for vsg, v1?6, hd/vd, mshut, strobe, sync, and serial interface 50 hd dio horizontal sync pulse (input for slave mode, output for master mode) 51 dclk do data clock output 52 nc not internally connected 53 nc not internally connected 54 d0 do data output (lsb) 55 d1 do data output 56 d2 do data output notes 1 see figure 38 for circuit con guration. 2 ai = analog input, ao = analog output, di = digital input, do = digital output, dio = digital input/output, p = power. pin function descriptions 1 rev. 0 AD9991 ?7? terminology differential nonlinearity (dnl) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. thus every code must have a nite width. no missing codes guaranteed to 10-bit resolution indicates that all 1024 codes must be present ov er all operating conditions. p eak nonlinearity p eak nonlinearity, a full signal chain speci cation, refers to the peak deviation of the output of the AD9991 from a true straight line. the point used as zero scale occurs 0.5 lsb before the rst code transition. positive full scale is de ned as a level 1.5 lsb beyond the last code transition. the deviation is measured from the middle of each particular output code to the true straight line. the error is then expressed as a p ercent- age of the 2 v adc full-scale signal. the input signal is always appropriately gained up to ll the adc s full-scale range. t otal output noise the rms output noise is measured using histogram techniques. the standard deviation of the adc output codes is calculated in lsb and represents the rms noise level of the total signal chain at the speci ed gain setting. the output noise can be converted to an equivalent voltage using the relationship 1 lsb = (adc full scale/2 n codes), where n is the bit resolution of the adc. for the AD9991, 1 lsb is 1.95 mv. po w er supply rejection (psr) the psr is measured with a step change applied to the supply pins. the psr speci cation is calculated from the change in the data outputs for a given step change in the supply voltage. equivalent circuits r av d d a vss avss circuit 1. ccdin dvdd d vss drvss drvdd three- state data dout circuit 2. digital data outputs dvdd d vss circuit 3. digital inputs hvdd or rgvdd hvss or rgvss outpu t rg, h1?4 enable circuit 4. h1?h4, rg drivers rev. 0 ?8? AD9991?typical performance characteristics sample rate (mhz) 350 250 100 10 power dissipation (mw) 150 200 300 15 v dd = 3.3v v dd = 3.0v 21 v dd = 2.7v 27 to ta l h1-4 load = 400 pf tpc 1. power dissipation vs. sample rate 1.0 0 1000 400 200 600 800 0.5 0 0.5 1.0 dnl (lsb) codes tpc 2. typical dnl performance vga gain code (lsb) 0 0 1000 400 output noise (lsb) 200 2.5 600 800 5 7.5 10 tpc 3. output noise vs. vga gain rev. 0 AD9991 ?9? system overview figure 1 shows the typical system block diagram for the AD9991 used in master mode. the ccd output is processed by the AD9991? afe circuitry, which consists of a cds, vga, black level clamp, and a/d converter. the digitized pixel information is sent to the digital image processor chip, which performs the postprocessing and compression. to operate the ccd, all ccd timing parameters are programmed into the AD9991 from the system microprocessor through the 3-wire serial interface. from the system master clock, cli, provided by the image processor or external crystal, the AD9991 generates all of the ccd? hori- zontal and vertical clocks and all internal afe clocks. external synchronization is provided by a sync pulse from the micropro- cessor, which will reset internal counters and resync the vd and hd outputs. alternatively, the AD9991 may be operated in slave mode, in which vd and hd are provided externally from the image pro- cessor. in this mode, all AD9991 timing will be synchronized with vd and hd. ccdin mshut strobe h1 h4, rg, vsub v1 v6, vsg1 vsg5, subck ccd v- driver AD9991 afetg digital image processing asic dout dclk hd, vd cli serial interface sync figure 1. typical system block diagram, master mode the h-drivers for h1?4 and rg are included in the AD9991, allowing these clocks to be directly connected to the ccd. h-drive voltage of up to 3.3 v is supported. an external v-driver is required for the vertical transfer clocks, the sensor gate pulses, and the substrate clock. the AD9991 also includes programmable mshut and strobe outputs, which may be used to trigger mechanical shutter and strobe ( ash) circuitry. figures 2 and 3 show the maximum horizontal and vertical counter dimensions for the AD9991. all internal horizontal and ve r tical clocking is controlled by these counters to specify line and pixel locations. maximum hd length is 4095 pixels per line, and maximum vd length is 4095 lines per eld. 12-bit horizontal = 4096 pixels max 12-bit vertical = 4096 lines max maximum field dimensions figure 2. vertical and horizontal counters vd hd max vd length is 4095 lines cli max hd length is 4095 pixels figure 3. maximum vd/hd dimensions rev. 0 AD9991 ?10? precision timing high speed timing generation the AD9991 generates high speed timing signals using the exible precision timing core. this core is the foundation for generating the timing used for both the ccd and the afe: the reset gate rg, horizontal drivers h1?4, and the shp/shd sample clocks. a unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal ccd readout and the afe correlated double sampling. the high speed timing of the AD9991 operates the same in either master or slave mode con guration. for more information on synchronization and pipeline delays, see the power-up and syn- chronization section. timing resolution the precision timing core uses a 1 master clock input (cli) as a reference. this clock should be the same as the ccd pixel clock frequency. figure 4 illustrates how the internal timing core divides the master clock period into 48 steps or edge positions. using a 20 mhz cli frequency, the edge resolution of the preci- sion timing core is 1 ns. if a 1 system clock is not available, it is also possible to use a 2 reference clock by programming the clidivide register (addr 0x30). the AD9991 will then inter- nally divide the cli frequency by 2. the AD9991 also includes a master clock output, clo, which is the inverse of cli. this output is intended to be used as a crystal driver. a crystal can be placed between the cli and clo pins to generate the master clock for the AD9991. for more information on using a crystal, see figure 39. high speed clock programmability figure 5 shows how the high speed clocks rg, h1?4, shp, and shd are generated. the rg pulse has programmable rising and fa lling edges, and may be inverted using the polarity control. the horizontal clocks h1 and h3 have programmable rising and fall- ing edges and polarity control. the h2 and h4 clocks are always inverses of h1 and h3, respectively. table i summarizes the high speed timing registers and their parameters. figure 6 shows the typical 2-phase h-clock arrangement in which h3 and h4 are programmed for the same edge location as h1 and h2. the edge location registers are six bits wide, but there are only 48 v alid edge locations available. therefore, the register values aremapped into four quadrants, with each quadrant containing notes pixel clock period is divided into 48 positions, providing fine edge resolution for high speed clocks. there is a fixed delay from the cli input to the internal pixel period positions ( t clidly = 6ns typ). p[0] p[48] = p[0] p[12] p[24] p[36] 1 pixel period cli t clidly position figure 4. high speed clock resolution from cli master clock input h1 h2 ccd signal rg programmable clock positions: 1. rg rising edge 2. rg falling edge 3. shp sample location 4. shd sample location 5. h1 rising edge position 7. h3 rising edge position h3 h4 3 4 12 56 78 6. h1 falling edge position (h2 is inverse of h1) 8. h3 falling edge position (h4 is inverse of h3) figure 5. high speed clock programmable locations rev. 0 AD9991 ?11? 12 edge locations. table ii shows the correct register values for the corresponding edge locations. figure 7 shows the default timing locations for all of the high speed clock signals. h-driver and rg outputs in addition to the programmable timing positions, the AD9991 features on-chip output drivers for the rg and h1?4 outputs. these drivers are powerful enough to directly drive the ccd inputs. the h-driver and rg current can be adjusted for optimum rise/fall time into a particular load by using the drvcontrol register (addr 0x35). the 3-bit drive setting for each output is adjustable in 4.1 ma increments, with the minimum setting of 0 equal to off or three-state, and the maximum setting of 7 equal to 30.1 ma. as shown in figures 5, 6, and 7, the h2 and h4 outputs are in verses of h1 and h3, respectively. the h1/h2 crossover volt- age is approximately 50% of the output swing. the crossover voltage is not programmable. digital data outputs the AD9991 data output and dclk phases are programmable using the doutphase register (addr 0x37, bits [5:0]). any edge from 0 to 47 may be programmed, as shown in figure 8a. normally, the dout and dclk signals will track in phase based on the doutphase register contents. the dclk output phase can also be held xed with respect to the data outputs by chang- ing the dclkmode register high (addr 0x37, bit 6). in this mode, the dclk output will remain at a x ed phase equal to clo (the inverse of cli) while the data output phase is still programmable. there is a x ed output delay from the dclk rising edge to the dout transition, called t od . this delay can be programmed to four values between 0 ns and 12 ns, by using the doutdelay register (addr 0x037, bits [8:7]). the default value is 8 ns. the pipeline delay through the AD9991 is shown in figure 8b. after the ccd input is sampled by shd, there is an 11-cycle delay until the data is available. ta b le i. timing core register parameters for h1, h3, rg, shp/shd p arameter length range description p olarity 1b high/low polarity control for h1, h3, and rg (0 = no inversion, 1 = inversion) p ositive edge 6b 0?7 edge location positive edge location for h1, h3, and rg negative edge 6b 0?7 edge location negative edge location for h1, h3, and rg sampling location 6b 0-47 edge location sampling location for internal shp and shd signals drive strength 3b 0?7 current steps drive current for h1?4 and rg outputs (4.1 ma per ste p) h1/h3 h2/h4 rg using the same toggle positions for h1 and h3 generates standard 2-phase h-clocking. ccd signal figure 6. 2-phase h-clock operation ta b le ii. precision timing edge locations quadrant edge location (dec) register value (dec) register value (b in) i 0 to 11 0 to 11 000000 to 001011 ii 12 to 23 16 to 27 010000 to 011011 iii 24 to 35 32 to 43 100000 to 101011 iv 36 to 47 48 to 59 110000 to 111011 rev. 0 AD9991 ?12? p[0] pixel period rg h1/h3 rgf[12] p[48] = p[0] hf[24] ccd signal p[24] p[12] p[36] hr[0] rgr[0] shd[0] notes all signal edges are fully programmable to any of the 48 positions within one pixel period. default positions for each signal are shown. position t s1 h2/h4 shp[24] figure 7. high speed timing default locations notes data output (dout) and dclk phase are adjustable with respect to the pixel period. within one clock period, the data transition can be programmed to 48 different locations. output delay ( t od ) from dclk rising edge to dout rising edge is programmable. p[0] p[48] = p[0] pixel period p[12] p[24] p[36] dout dclk t od figure 8a. digital output phase adjustment notes default timing values are shown: shdloc = 0, dout phase = 0, dclkmode = 0. higher values of shd and/or doutphase will shift dout transition to the right, with respect to cli location. dclk dout ccdin cli shd (internal) n n+1 n+2 n+12 n+11 n+10 n+9 n+8 n+7 n+6 n+5 n+4 n+3 n+13 n-13 n-3 n-4 n-5 n-6 n-7 n-8 n-9 n-10 n-11 n-12 n-2 n-1 n+1 n sample pixel n pipeline latency=11 cycles t clidly n-1 n+2 figure 8b. pipeline delay rev. 0 AD9991 ?13? horizontal clamping and blanking the AD9991 |